1. Field of the Invention
The present invention relates to ESD protection circuits, and particularly to ESD protection circuits with uniform turn-on design on multiple-finger MOSFET for ESD protection.
2. Description of the Related Art
A NMOS is an effective ESD protection device, which is based on snapback mechanism. Snapback mechanism enables the NMOS to conduct a high level of ESD current between its drain and source while an ESD zapping occurs. But, there is a weakness of the NMOS for ESD protection caused by the low snapback voltage of the parasitic NPN of the NMOS, which leads to second breakdown, which in turn leads to filamentation and subsequently to permanent damage to transistor. During snapback, the current is conducted uniformly by all the fingers of the NMOS and the snapback device current scales linearly with the device width. This scaling is possible because during snapback the resistance has a positive temperature coefficient of resistance. Thus, if the current in any region increases, that region gets hot, thereby increasing the resistance, which promote the current to flow elsewhere. However, with the onset of second breakdown, the resistance of the current path has a negative temperature coefficient dependence, encouraging current hogging and filament formation. This non-uniformity in current distribution essentially concentrates the current in certain localized regions of the NMOS. Thus, the discharge potential of the current cannot be fully developed.
FIG. 1 shows the layout top-view of traditional multi-finger gate-grounded NMOS (GGNMOS) or gate-VDD PMOS for ESD protection design. FIG. 2 shows the schematic of the multi-finger GGNMOS. The drains of the MOSFETs are connected to the pad. The sources and gates of the MOSFET are connected to the ground (VSS). All of the MOSFETs are in parallel. FIG. 3(a) shows the equivalent circuit of the multi-finger GGNMOS, and the cross-sectional view is shown in FIG. 3(b). Because of the center finger has the farthest spacing to the guard ring, then the equivalent substrate resistance Rsub is the largest. The substrate resistance Rsub of every finger is different. This often causes the non-uniform turn-on issue on the multiple-finger NMOS device in the ESD protection circuit.
FIG. 4(a) shows the snapback I-V curve of the GGNMOS. When the parasitic lateral bipolar is turned on under the ESD event, the snapback phenomenon is happened. If one of the multiple fingers is turned on first, then the operating voltage is pulled down to the holding voltage and the other fingers will not be turned on. Therefore, the ESD level will not increase as the finger number increased. This is the non-uniform turn-on effect shown in FIG. 4(b). The ESD level can not be continually increased when the device width is increased.
FIG. 5 shows the turn-on behavior of the multi-finger GGNMOS under ESD stress. At point A, there is no ESD pulse and the GGNMOS is kept off under normal condition. At point B-point D, when the ESD pulse is increased, the GGNMOS is still kept off because of the gates are connected to the ground without channel induced. At point E-point F, when the ESD pulse is increased, the breakdown at the drain side is occurred and the parasitic lateral BJT at center is triggered on and the snapback effect is occurred. Therefore, the other fingers will not be turned on and the ESD current will flow through the turned-on fingers to the ground. This is the so called non-uniform turn-on phenomenon of the multi-finger MOSFETs. At point G-point J, when the ESD pulse is more increased, the fingers closed to the center are fully turned on, but the fingers far away the center are still kept off. With only few fingers turned on during ESD zapping, the NMOS will have a low ESD robustness even if the NMOS is drawn with larger device dimension.
In order to solve the non-uniform turn-on issue, the drain and source resistance (Rd and Rs) are used in FIG. 6. For example, when finger F2 is triggered, a potential Vsi2 is built. The potential is presented to the gate of the finger F3. As long as no current flows through F3, Vsi3 will be zero, and thus a bias Vgs3 will exist. When Vgs3 exceeds the threshold voltage of the NMOS, finger F3 will be fully turned on. The same mechanism will create a “domino effect” that will turn on all fingers one after the other.
The ESD protection circuits mentioned above usually does not turn on uniformly. There is a need for an ESD protection circuit with the property of turning on uniformly. Assuring that at least a finger is turn on initially, the other fingers are definitely triggered turning on by it. Thus, ESD susceptibility of integrated circuits is improved.